Bumping & Backside Metallization (BSM)
The world is now enjoying 5G+ and AI technology, and TF-AMD is proud to be one of the key technology contributors. At TF-AMD Penang, we offer an Advanced Packaging Platform featuring Bumping & BSM. Bumping & BSM are advanced wafer-level packaging (WLP) technologies that significantly improves performance over traditional packaging methods. It covers three major technologies
ubump, including uStud, with or without Polyimide (PI) Repassivation.
Copper bump, including Cu+SnAg or Cu+Ni+SnAg, or Cu+Ni+Cu+SnAg
Back Side Metallization (BSM), including Al+Ti+NiV+Au or Ti+NiV+Au.
This product solution uses copper pillars to form the interconnection between the integrated circuit (IC) and the motherboard (or lead frame). It meets the demands of the growing global consumer marketplace for portable electronics
Bumping & BSM Features
| Wafer Size: | 12” |
| Wafer Node: | 4nm and above |
| Die Size: | Below 20x40mm |
| Bump structure: | 0P1M, 1P1M |
| Pillar bump: | Cu+SnAg & Cu+Ni+SnAg |
| PI Material: | HD4104 & BM406HB |
| PI CD: | ≥15um |
| Bump P/S: | 45um/25um |
Reliability Test Standards
The test criterion is zero defect out of 77 sampling units.
JEDEC Precondition MSL-1：J-STD-20/JESD22-A113
| Temp/Humidity Test | 85°C/ 85% RH, 1000hrs, JEDEC 22- A101 |
| Pressure Cooker Test | 121°C/ 100% RH/ 15 PSIG, 96hrs, JEDEC 22- A102 |
| Temp Cycle Test | -65 ~ 150°C, 500cycles, JEDEC22-A104 |
| High Temp Storage Test | 150°C, 1000hrs, JEDEC 22- A103 |